The present invention relates in general to semiconductor manufacturing. More particularly, it relates to an interconnect architecture with improved reliability and a method for fabricating the same, most suitably for the 65 nm technology node and beyond.
Integrated circuits (ICs) typically include metal wiring connecting different regions of the circuit. The metal wiring is insulated by a dielectric material in order to prevent capacitance coupling, leakage, or cross-talk between the electrical pathways. Metal wiring forming the interlevel connection are commonly referred to as interconnects and are formed by depositing a metal in an opening such as a via, a hole, or a trench. The metallic interconnect is typically fabricated using damascene or dual damascene technique.
With continuing device scaling beyond the 90 nm node, wiring interconnection becomes increasingly important in limiting chip density and performance. Fundamental changes in interconnect materials are needed with Cu replacing Al and low permittivity dielectrics replacing silicon dioxide. The integration of these two advanced materials has resulted in significant reduction in signal delay, cross-talk and power dissipation, enabling the semiconductor industry to continue device scaling. The fabrication of Cu/low k interconnects requires novel materials and processes, including electroplating with Cu, dual damascene structures, chemical-mechanical polishing (CMP), ultra-thin barriers and passivation layers. The novel materials and processes have given rise to distinct structure and defect characteristics raising yield and reliability concerns for Cu/low k interconnects. As the technology continues to advance, the CMP of Cu interconnects beyond the 65 nm node has brought new processing and reliability issues.
The invention is generally directed to a novel interconnect architecture for improvement of reliability.